1. Field of the Invention
The invention relates to a sampling circuit system wherein sampling resolution can be enhanced without increasing the frequencies of clock signals for sampling an input waveform.
2. Description of the Related Art
FIG. 2 shows a block diagram of a conventional sampling circuit for sampling an input waveform with a clock signal. In FIG. 2, a case is shown wherein a D type flip-flop (referred to hereinafter as DFF) is used for a sampling circuit.
In FIG. 2, an input waveform 1, a signal to be sampled, is inputted to an input terminal D of a DFF 4, and the input waveform 1 is sampled by inputting a clock signal 2 at a predetermined frequency to a clock terminal CK thereof, and a sampling waveform 3 is outputted from an output terminal Q of the DFF 4.
In the conventional sampling circuit described above, however, there is a problem that a frequency of the clock signal 2 needs to be increased in order to enhance sampling resolution.